BSIM3 – TechConnect Briefs

Modeling Snapback and Rise-time Effects in TLP Testing for ESD MOS Devices using BSIM3 and VBIC Models

Zhou Y., Connerney D., Carroll R., Luk T., Fairchild Semiconductor, US

A simple SPICE macro model has been created for ESD MOS modeling. The model consists of standard components only. It includes a MOS transistor modeled by BSIM3v3, a bipolar transistor modeled by VBIC, and a [...]

Automatic BSIM3/4 Model Parameter Extraction with Penalty Functions

Mahotin Y., Lyumkis E., Integrated Systems Engineering, Inc., US

The first successful automatic extraction of BSIM3/4 model parameters based on numerical optimization of a functional, which includes penalty functions, is reported. The penalty functions always keep the values of the model parameters within a [...]

Detailed Comparison of the SP2001, EKV, and BSIM3 Models

Bendix P., LSI Logic, US

Practical comparisons are made of three available or soon to be available compact MOS models----SP2001 (surface potential 2001), EKV, and BSIM3. They are compared both in their DC and AC quality of fits to measured [...]

Extraction of Compact Model Parameters for ULSI MOSFETs Using a Genetic Algorithm

Watts J., Bittner C., Heaberlin D., Hoffman J., IBM Microelectronics Division, US

Extracting an optimal set of parameter values for an FET device model is a complex problem. The final model must not only describe the performance of a set of hardware to an acceptable level of [...]