analog – TechConnect Briefs

An SOA Aware MOSFET Model for Highly Integrated, Analog Mixed-Signal Design Environments

Hall J., Luo Z., Xiao Y., Young A., Connerney D., Fairchild Semiconductor, US

Circuit simulations involving power devices often require additional checks comparing with generic low power applications. The burden lies with the individual designers to ensure that the power transistors are operating well within the Safe Operating [...]

Compare and Contrast HiSIM-LDMOS and BSIM based compact model of High Voltage MOSFETs for Analog Applications

Young A., Hall J., Luo Z., Xiao Y., Connerney D., Fairchild Semiconductor, US

A pair of scalable spectre models, one utilizes the Surface Potential based HiSIM-LDMOS model, and the other, the conventional Vth-based BSIM3v3 model, were extracted based on a test vehicle designed with both Drain-Extended CMOS and [...]

Castellated-Gate MOSFETs as Power Transistors for Nanometer CMOS and Post-CMOS Integrated Nanosystems

Seliskar J.J., HiperSem Inc., US

Analysis of the constant-voltage scaling characteristics of Fully-Depleted Castellated Gate (FDCG) MOSFETs reveals near term opportunities for these devices as the replacement for the “thick oxide” I/O device in CMOS System-On-A-Chip (SoC) technologies (e.g. the [...]

Keywords: analog

An SOA Aware MOSFET Model for Highly Integrated, Analog Mixed-Signal Design Environments

Compare and Contrast HiSIM-LDMOS and BSIM based compact model of High Voltage MOSFETs for Analog Applications

Castellated-Gate MOSFETs as Power Transistors for Nanometer CMOS and Post-CMOS Integrated Nanosystems

Model Implementation for Accurate Variation Estimation of Analog Parameters in Advanced SOI Technologies

How To Design for Analog Yield using Monte Carlo Mismatch SPICE Models

New Capabilities for Verilog-A Implementations of Compact Device Models

Spice-like Simulation Using Real Devices Instead of their Mathematical Models