Yu S-M. – TechConnect Briefs

A Simulation-Based Hybrid Optimization Technique for Low Noise Amplifier Integrated Circuit Design Automation

Li Y., Yu S-M., National Chaio Tung University, TW

In this paper we propose an intelligent simulation-based optimization technique for designing low noise amplifier (LNA) integrated circuits (ICs). Based on a genetic algorithm (GA), the Levenberg–Marquardt (LM) method, and a circuit simulator, the hybrid [...]

Random Discrete Dopant Fluctuated Sub-32 nm FinFET Devices

Li Y., Hwang C-H, Yu S-M., Huang H.M., Chen H-M, National Chaio Tung University, TW

Scaling of silicon production technology has approached the sub-65nm regime. Device’s electrical characteristics fluctuate according to the discreteness and randomness of dopants in sub-32nm technologies. In this paper, we investigate the random-dopant-induced electrical characteristics fluctuations, [...]

A Parallel Intelligent OPC Technique for Design and Fabrication of VLSI Circuit

Yu S-M., Li Y., National Chiao Tung University, TW

Optical lithography is the key technology used in very large scale integrated (VLSI) circuit and systemon- a-chip (SoC) fabrication [1-3]. The exposure on wafer has distortions due to the proximity effects. Hence, a correction of [...]

Parallel Dynamic Load Balancing for Semiconductor Device Simulations on a Linux Cluster

Li Y., Lin S-S., Liu J-L., Lin S-S., Yu S-M., Liu J-L., Chao T-S., Sze S.M., National Chiao Tung University, TW

A parallel dynamic load balancing for 2-D and 3-D semiconductor device simulations is proposed. The hydrodynamic and drift diffusion models are discretized and solved with finite volume (box) and monotone iterative methods. Dynamic load balancing [...]