Sidek O. – TechConnect Briefs

SPICE Modeling of Hook Shaped Idsat Curve for I/O 2.5V MOS Transistors

Tan P.B.Y., Kordesch A.V., Sidek O., Silterra Malaysia Sdn Bhd, MY

In this paper, we demonstrated how we have modified the mobility equation to accurately model the I-V characteristics of I/O 2.5V MOS transistors. Our aim is to model the effect of mechanical STI stress in [...]

How To Design for Analog Yield using Monte Carlo Mismatch SPICE Models

Tan P.B.Y., Kordesch A.V., Sidek O., Silterra Malaysia Sdn Bhd, MY

The downscaling of devices causes the unpredictability of analog circuit yield. Transistor mismatch is one of the obstacles to achieving high yield. Analog circuit designers usually run Monte Carlo mismatch models to predict the functionality [...]

Mismatch Improvement with XMOS Structure

Tan P.B.Y., Kordesch A.V., Sidek O., Silterra Malaysia Sdn Bhd, MY

MOS transistor has been continuously scaled down to improve the device performance. Smaller MOS transistors have higher transconductance (gm) and low capacitance, so the ratio gm/C is improved by shrinking. Shorter gate length provides higher [...]

Simplified Half-Flash CMOS Analog-to-Digital Conveter

Tan P.B.Y., Kordesch A.V., Sidek O., Silterra Malaysia, MY

In this paper, we present a simplified method to construct a half-flash analog-to-digital converter (ADC) to achieve less die area consumption compared to the conventional half-flash ADC. Although the die area consumption is reduced but [...]