A novel simulation methodology for full chip-package thermo-mechanical reliability investigations
Karunamurthy B., Ostermann T., Bhattacharya M., KAI Kompetenzzentrum Automobil- und Industrieelektronik GmbH, AT
A methodology for simulating the accurate structural details of a non-planarized technology chips is presented. This approach uses a virtual semiconductor fabrication technique to create geometry and finite element mesh on complex chip topology features. [...]