Wang T., Bennaser M., Guo Y., Moritz C.A.
University of Massachusetts Amherst, US
Keywords: architecture, fault tolerance, NASIC, silicon nanowires
One of the most promising underlying nanodevice technologies today for nanoscale integrated circuits are semiconductor nanowires (NWs) and arrays of crossed NWs. Researchers have already built FETs and diodes out of NWs. There has also been a lot of progress made on assembling arrays of such devices with both lithographic techniques and bottom-up self-assembly. In this paper, we describe our initial architectural design based on self-healing circuits and architectures using 2-D semiconductor NWs. We also provide an overview of how the design can be manufactured with a combination of bottom-up self-assembly and top-down lithography. Our approach provides significant advantages compared to other fabrics like NanoPLA, NanoFabrics, and CMOL. These advantages include self-healing circuits and thus elimination of the challenging step to access all crosspoints to extract a defect map, as well as reconfiguration, much higher density with unique circuits on the 2-D fabric, and a design that scales with improvements in nanofabrication as opposed to being limited by CMOS. We also provide a comparison with an equivalent processor implemented in Verilog, synthesized to CMOS, and scaled to 35 and 18-nm technology as projected by ITRS. Finally, we discuss advantages compared to other nanoscale fabrics.
Journal: TechConnect Briefs
Volume: 3, Technical Proceedings of the 2006 NSTI Nanotechnology Conference and Trade Show, Volume 3
Published: May 7, 2006
Pages: 312 - 315
Industry sector: Advanced Materials & Manufacturing
Topic: Advanced Manufacturing
ISBN: 0-9767985-8-1