Jastrzebski R., Napieralski A., Pyrhonen O., Saren H.
Technical University of Lodz, PL
Keywords: ciruits
DTC (Direct Torque Control) techniques incorporating fast microprocessors and DSPs have made possible the application of AC motors for high-performance applications where traditionally the DC motors were applied. In this paper the DTC algorithm implemented in affordable FPGA with use of relatively simple tools, is presented. Direct-Torque-Control is a model-based control. Direct torque is achieved by direct and independent control of the flux linkages and electromagnetic torque. These are obtained through the selection of optimal inverter switching which gives fast torque response, low inverter switching frequency, and low harmonic losses. The aim of the paper is to present the DTC design (close control loop T < 5ìs) and the interface of the wider motor control system, everything on a single chip. In this work, in contrast to microprocessor-based control, the HDL design for motor control is presented. Particularly inverter control system algorithms like: communication, data processing, filtering, control testing and DTC core computing are implemented in the SPARTAN II 50k gates, XILINX’s FPGA circuit. Implementation’s main goal was area optimization to fit into cheapest FPGA, the solution was to design small sequential, arithmetic operations unit that shares calculation resources for other modules. Implemented arithmetic unit can be denoted as simple embedded microprocessor with reduced instruction set (multiplying, summing, subtracting and comparison, per clock cycle). In the DTC core to meet the design requirements the flux and torque comparators, switching table, eliminating offset calculations and computing current and voltage reduced values, were made in the hardware. On the other hand, the implemented embedded microprocessor unit executes all remaining arithmetic calculations. What is more the flux integration was realized by adding extended bit width registers for estimated flux vector complex components, to increase integration accuracy. The DTC-core block presents Figure 1. The experimental algorithms’ results were tested using development board that contained XC2S100-5PQ208 FPGA. But to final implementation target XC2S50 (50k gates, about 8-10 per chip) was chosen. The communication algorithms (interface module between measuring current and DC link voltage devices and DTC controller) were tested in the real system. The simulation results of implemented DTC computing core in one chip was evaluated by comparing to previously designed and tested Matlab Simulink model that is working in the lab environment (in the very same system as communication algorithms). Figures 2 to 4 present compared results for both models. Today, DTC control tested in the system has a 25ìs fastest control loop. With implemented in FPGA DTC core the fastest control loop is up to 1,6ìs.
Journal: TechConnect Briefs
Volume: 2, Technical Proceedings of the 2003 Nanotechnology Conference and Trade Show, Volume 2
Published: February 23, 2003
Pages: 238 - 241
Industry sector: Sensors, MEMS, Electronics
Topic: Nanoelectronics
ISBN: 0-9728422-1-7